The present invention relates to a semiconductor device having I/O amplifier circuits and electrodes disposed around its fringes and, more particularly, to a logic circuit semiconductor device that needs numerous input/output terminals.
The logic circuit semiconductor device is generally indicated by reference numeral 1 in FIG. 6. Generally, this semiconductor device 1 has the functional portion 2 of a logic circuit, the functional portions 3 of input/output amplifier circuits disposed around the functional portion 2, and electrodes 4 for making connections with an external substrate (not shown).
The electrodes 4 are disposed around fringes of the semiconductor device so as to correspond to their respective input/output amplifier circuits in a 1:1 relation. If necessary, the input/output amplifier circuits are electrically connected with their respective electrodes.
The logic circuit semiconductor device 1 is installed on a package equipped with external terminals which are connected with the external substrate. The device 1 is tied with signal lead lines existing inside the package via the electrodes and is also electrically connected with the external substrate via the external terminals. The logic circuit semiconductor device is connected with the signal lead lines by ball bonding using Au wires or by TAB bonding (tape automated bonding) using TAB tape.
This logic circuit semiconductor device is isolated from other logic circuit semiconductor devices at a scribe center 5. The functional portions 3 of the input/output amplifier circuits are formed by input/output amplifier circuits 6.
In recent years, as semiconductor fabrication technology develops, miniaturization of semiconductor devices has improved greatly. Also, device densities has increased greatly. As a result, it has been possible to fabricate large-scale integrated logic circuitry out of semiconductor devices. As semiconductor device densities are increased, it has been required to offer semiconductor devices which permit one to select the ratios of the numbers of leads and electrodes to the size of the circuit of semiconductor devices according to the sizes of the circuits of the electronic appliance or apparatus from various values.
This tendency is conspicuous in cases of application-specific integrated circuits (ASICs) such as gate arrays and standard cells. Especially, in the case of gate arrays, it is important that semiconductor devices installed on the arrays and connectable electrodes be selected from a wide choice of numbers. Furthermore, it is necessary that the semiconductor devices be inexpensive.
As semiconductor device size has become smaller and device densities have increased, a semiconductor device which forms small-scale circuitry or has small size and which is equipped with numerous connected electrodes has generally been required.
In order to satisfy this requirement, it is important that means for connecting a semiconductor device with signal lines inside a package be made thinner. In particular, fabrication technology for interconnecting small semiconductor elements having numerous electrodes closely spaced from each other and for assembling a semiconductor device, especially up to a molded semiconductor device, using the interconnected elements, is important. In addition, the interconnecting means are required to be economical.
As mentioned previously, in the case of a molded semiconductor device, ball bonding and TAB bonding are generally used to interconnect a semiconductor device having logic circuitry and signal lines inside a package. In the case of a semiconductor device having numerous interconnected electrodes, it is essential to use ball bonding and TAB bonding adequately according to the purpose in order to maintain the performance and to seek for good economy as described below.
We now take a conventional molded semiconductor device as an example. Where interconnections are made by ball bonding, leadframes are installed around a semiconductor device. The front ends of the inner leads of the leadframes are connected with the electrodes formed on top of the semiconductor device by Au wires.
The positional relation between the front ends of the inner leads and the electrodes are physically determined by the number of the leads and by the pitch between the front ends of the leads. Specifically, when the leads are machined, if the pitch between the front ends can be narrowed, then the front ends of the inner leads can be brought closer to the semiconductor device even if the number of the leads is larger. However, the pitch between the front ends can be reduced to about 200 .mu.m at best because of the minimum size achievable by etching techniques or presswork techniques.
Therefore, where a subminiature semiconductor device having numerous electrodes spaced less than 200 .mu.m from each other is connected with an external substrate by Au wires, the inner leads are spaced remotely from the corresponding leads. Consequently, the distance between the electrodes and the front ends of the corresponding inner leads is increased. This increases the lengths of the loops formed by the Au wires.
Where the lengths of the loops formed by the Au wires are increased, the diameter of the Au wires must be increased to prevent them from warping or sagging. On the other hand, in order to connect closely spaced electrodes by ball bonding, the diameter of the Au wires must be reduced. Accordingly, where a small-sized semiconductor device having numerous electrodes spaced less than 200 .mu.m from each other is connected with an external substrate by Au wires, it is necessary to satisfy these two conflicting technical requirements.
Where ball bonding is done, the capillaries of a bonding machine are not permitted to contact adjacent Au wires shaped like nail heads. The capillaries are Jigs for crushing a ball formed at the head of each Au wire and shaping the ball into a form resembling a nail head. Therefore, even if an optimum capillary shape is used, it is impossible to increase the Au wire diameter beyond a certain value. Hence, it is impossible to reduce the electrode spacing below a certain value. Because of these conditions, if it is assumed that the minimum achievable wire diameter is about 30 .mu.m, then the minimum achievable electrode spacing is 95 to 100 .mu.m.
Although the loop lengths of Au wires, the electrode spacing, and the pitch between the front ends of the inner electrodes have technical limitations as described above, the greatest advantage of ball bonding is that it is inexpensive. Because of the economy, use of ball bonding is required as long as it can be applied technically.
Meanwhile, where interconnections are made by TAB bonding, the accuracy at which fingers on a TAB film are aligned with bumps formed on electrodes and the accuracy at which they are fabricated are limiting factors. Since dimensional limitations such as the loop lengths of Au wires, the electrode spacing, and the pitch between the front ends of the inner electrodes as encountered in the above-described ball bonding do not exist, the electrode spacing can be reduced down to 60-70 .mu.m.
For this reason, for a subminiature semiconductor device which has electrodes closely spaced from each other and to which the ball bonding cannot be applied, interconnections can be made by TAB bonding. However, the cost is high, because expensive TAB film and bumps must be employed. In consequence, it is necessary that ball bonding and TAB bonding be used properly, depending on the purpose, from technical and economical points of view.
With respect to the circuit arrangements of a semiconductor device, especially the circuit arrangements of ASICs, the functional portions of logic circuits have become smaller and smaller because of development of microminiaturization technology. However, input/output amplifier circuit portions around the functional portions of logic circuits have required the same areas as used in the prior art techniques in order to secure sufficient ability to drive the devices. That is, the input/output amplifier circuit portions cannot be reduced in size though the functional portions of logic circuits become smaller and smaller. This technical gap has grown increasingly.
To permit ball bonding and TAB bonding to be used properly, depending on the purpose, subassemblies each consisting of an input/output amplifier circuit and an electrode must be designed and fabricated separately. This requirement is not permitted in designing and fabrication of ASICs such as gate arrays.
Where it is attempted to permit ball bonding and TAB bonding to be used properly, depending on the purpose, and to arrange electrodes in or on the same semiconductor device with an electrode spacing close to the minimum values achievable by both ball bonding and TAB bonding, it is necessary to determine the size of the semiconductor device with the lowest multiple common to both minimum achievable electrode spacings. This makes it impossible to fabricate semiconductor devices with any arbitrary size.